Phase-lock assistant circuitry

ABSTRACT

Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

RELATED APPLICATIONS

The present application is a broadening reissue of U.S. patentapplication Ser. No. 12/835,130, filed Jul. 13, 2010, now U.S. Pat. No.8,179,162, issued May 15, 2012, the content of which is herebyincorporated by reference herein in its entirety.

TECHNICAL FIELD

The present disclosure is generally related to phase-lock-loop basedclock-data recovery (PLL-based CDR) circuitry, and more specifically toa phase-lock assistant circuit.

BACKGROUND

The clock-data recovery (CDR) circuitry based on a phase-lock loop (PLL)usually includes two loops. A first loop brings the frequency of thevoltage-controlled oscillator (VCO) (e.g., the CDR frequency) closer tothe frequency of the input data (e.g., the input frequency) while asecond loop locks the phase of the VCO into that of the input data. Insome approaches related to the two-loop structure using the spreadspectrum clock (SSC), however, if the input frequency varies at thetransition from the first loop to the second loop, the VCO does not lockinto the input data. As a result, there is a need to solve the aboveproblem.

BRIEF DESCRIPTION OF THE DRAWINGS

The details of one or more embodiments of the disclosure are set forthin the accompanying drawings and the description below. Other featuresand advantages will be apparent from the description, drawings, andclaims.

FIG. 1 is a diagram of an illustrative circuit, in accordance with someembodiments.

FIG. 2 is a graph of a waveform illustrating how a set of three phaseclocks and a data signal are used in determining the relative timingrelationship between the clock and the data signal in FIG. 1, inaccordance with some embodiments.

FIG. 3 is a graph of waveforms illustrating how the relative timingrelationship of the clock and the data signal in FIG. 1 is determinedusing multiple clock signals, in accordance with some embodiments.

FIG. 4 is a flowchart illustrating how signals are generated to adjustthe frequency of the output of the voltage-controlled oscillator in FIG.1, in accordance with some embodiments.

FIG. 5 is a diagram of a detailed circuit of the phase detector of FIG.1, in accordance with some embodiments.

FIGS. 6A-6D show truth tables illustrating an operation of the circuitin FIG. 5, in accordance with some embodiments.

FIG. 7 is a detailed block diagram of the phase lock assistant of FIG.1, in accordance with some embodiments.

FIG. 8 is a detailed block diagram of the circuit UPDOWN01 of FIG. 7, inaccordance with some embodiments.

FIG. 9 is a detailed circuit of circuit BB of FIG. 8, in accordance withsome embodiments.

FIGS. 10A-10C show truth tables illustrating an operation of the circuitin FIG. 8, in accordance with some embodiments.

FIG. 11 is a detailed circuit of the circuit UPDOWN in FIG. 7, inaccordance with some embodiments.

FIGS. 12A-12D show truth tables illustrating an operation of the circuitin FIG. 11, in accordance with some embodiments.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Embodiments, or examples, illustrated in the drawings are now disclosedusing specific language. It will nevertheless be understood that theembodiments and examples are not intended to be limiting. Anyalterations and modifications in the disclosed embodiments, and anyfurther applications of the principles disclosed in this document arecontemplated as would normally occur to one of ordinary skill in thepertinent art. Reference numbers may be repeated throughout theembodiments, but they do not require that feature(s) of one embodimentapply to another embodiment, even if they share the same referencenumber.

Some embodiments have one or a combination of the following featuresand/or advantages. Some embodiments include a phase-lock assistantcircuit that aligns the input data and the VCO output to improve thephase lock between the input data and the VCO output. Some embodimentsare used in applications with a SSC input and/or where there is adeviation between the frequency of the input data and the referenceclock, but the input and the VCO output are also locked.

Exemplary Circuit

FIG. 1 is a diagram of an exemplary CDR circuit 100 that uses someembodiments. CDR circuit 100 generates a clock (e.g., signal) OVCO basedon the input data IN. Those skilled in the art will recognize that afirst signal (e.g., a clock) having a frequency higher than that of asecond signal (e.g., data) indicates that the clock is faster than thedata. Similarly, the data having a frequency lower than that of theclock is slower than the clock. In contrast, the clock is earlier thanthe data if a relevant edge (e.g., the rising edge) of the clock isbefore a relevant edge of the data.

In some embodiments, signal OVCO generates eight phase clockscorresponding to eight phases, including phase 0° (e.g., Clk_0), phase45° (e.g., Clk_45), phase 90° (e.g., Clk_90), phase 135° (e.g.,Clk_135), phase 180° (e.g., Clk_180), phase 225° (e.g., Clk_225), phase270° (e.g., Clk_270), and phase 315° (e.g., Clk_315). Clocks Clk_0,Clk_45, Clk_90, Clk_135, Clk_180, Clk_(—225,) Clk_270 and Clk_315 run atthe same frequency but at different phases (e.g., different times). Inanother words, clocks Clk_0, Clk_45, Clk_90, Clk_135, Clk_180, Clk_225,Clk_270 and Clk_315 are in an order of being early to being late. Forexample, clock Clk_0 transitions earlier than clock Clk_45, clock Clk_45transitions earlier than clock Clk_90, clock Clk_90 transitions earlierthan clock Clk_135, etc.

Divide-by-N circuit DBN divides the frequency of signal OVCO (e.g.,frequency FOVCO, not labeled) by an integer N, resulting in frequencyFVCODBN where FVCODBN=FOVCO/N.

Phase frequency detector PFD enables outputfrequency FVCODBN of circuitDBN to be substantially close to (e.g., the same as) the frequency ofthe reference clock REFCLK (e.g., frequency FREFCLK). For example, ifclock OVCO is faster than clock REFCLK (e.g., frequency FVCODBN ishigher than frequency FREFCLK), then phase frequency detector PFDgenerates a “down” signal OPFD for charge pump PFD CP to drive low passfilter LPF to decrease frequency FVCO of oscillator VCO and thusfrequency FVCODBN. If clock OVCO is slower than clock REFCLK (e.g.,frequency FVCODBN is lower than frequency FREFCLK), phase frequencydetector PFD generates an “up” signal OPFD for charge pump PFD CP todrive low pass filter LPF to increase frequency FVCO and thus frequencyFVCODBN.

Phase detector PD enables the phase of input data IN (e.g., PHIN) to beclose to (e.g., the same as) the 90° phase of clock OVCO (i.e., therelevant data edge DE of input data IN to be close to (e.g., alignedwith) the rising edge of clock Clk_90). If clock OVCO is earlier thaninput data IN, phase detector PD generates a “down” signal OPD forcharge pump PD CP to drive low pass filter LPF to decrease frequencyFVCO. But if clock OVCO is later than input data IN, phase detector PDgenerates an “up” signal OPD for charge pump PD CP to drive low passfilter LPF to increase frequency FVCO. Decreasing or increasingfrequency FVCO respectively decreases or increases the frequency ofclock Clk_90, enabling the data edge DE to be aligned with the risingedge of clock Clk_90 (e.g., phase locking input data IN to clockClk_90).

In some situations, using only phase detector PD without a phaseassistant PLA to phase lock input data IN and clock Clk_90 enables adata edge DE to be close to but not completely aligned with the risingedge of clock Clk_90. Phase lock assistant PLA improves the phase lock,e.g., enables data edge DE to be (substantially) aligned with the risingedge of clock Clk_90. For example, If clock Clk_90 is earlier than inputdata IN, phase lock assistant PLA generates a “down” signal OPLA forcharge pump PLA CP to drive low pass filter LPF to decrease frequencyFVCO to slow down clock OVCO or clock Clk_90, and thus improves thephase lock. But if clock OVCO is later than input data IN, phase lockassistant PLA generates an “up” signal OPLA for charge pump PLA CP todrive low pass filter LPF to increase frequency FVCO to speed up clockOVCO or clock Clk_90, and thus improve the phase lock.

The charge pumps PLA CP, PFD CP, and PD CP function with the phase lockassistant PLA, phase frequency detector PFD, and phase detector PD,respectively. One of the charge pumps PLA CP, PFD CP, or PD CP,depending on the respective input signals OPLA, OPFD, or OPD, generatesthe appropriate signal OCP corresponding to each respective signal OPLA,OPFD, or OPD. FIG. 1 shows three charge pumps PLA CP, PFD CP, and PD CPin accordance with some embodiments, but, in accordance with somefurther embodiments, one charge pump (e.g., a charge pump CP) is used byall three phase lock assistant PLA, phase frequency detector PFD, andphase detector PD. For example, a multiplexer is used to select and thusprovides one of the outputs OPLA, OPFD, and OPD of the respective phaselock assistant PLA, phase frequency detector PFD, and phase detector PDto charge pump CP.

Signal OCP enables low pass filter LPF to generate signal OLPF toincrease/decrease frequency FOVCO.

Lock detector LD compares signal REFCLK and OVCO and generates a signalOLD to control phase lock assistant PLA, phase frequency detector PFD,and phase detector PD. In some embodiments, if frequency FVCODBN islocked to frequency FREFCLK, lock detector LD generates a “locked”signal OLD to turn off phase frequency detector PFD and turn onsimultaneously phase lock assistant PLA and phase detector PD. But iffrequency FVCODBN is not locked to frequency FREFCLK, lock detector LDgenerates a “not locked” signal OLD turn on phase frequency detector PFDand turn off simultaneously phase lock assistant PLA and phase detectorPD.

In some embodiments, frequency FVCODBN is locked to the frequency ofinput data IN (e.g., frequency FIN), and phase PHIN is aligned with(e.g., locked to) clock Clk_90 (e.g., the data edge DE is aligned withthe rising edge of clock Clk_90). When phase PHIN is locked to clockClk_90, input data IN is latched by clock OVCO having sufficient setupand hold time for clock OVCO.

Determining the Timing Relationship Between the Data and the Clock

FIG. 2 is a diagram of waveform 200 illustrating an operation of phasedetector PD, in accordance with some embodiments. Phase detector PDsamples input data IN by the rising edge of clock OVCO at three phases0°, 90°, and 180° represented by three respective clocks Clk_0, Clk_90,and Clk_180. In some embodiments, if the sampling result (e.g., RSMP90)of clock Clk_90 sampling input data IN is the same as the samplingresult RSMP0 of clock Clk_0 sampling input data IN, clock OVCO isearlier than input data IN, but if the sampling result RSMP90 is thesame as the sampling result RSM180 of clock Clk_180 sampling input dataIN then clock OVCO is later than input data IN. In the illustration ofFIG. 2, the sampling result RSMP0 is a logical “0” (e.g., a low logiclevel, a Low). The sampling result RSMP180 a logical “1” (e.g., a highlogic level, a High). As a result, if the sampling result RSMP90 isHigh, i.e., the same as the sampling result RSMP180, then clock OVCO islater than input data IN. But if the sampling result RSMP90 is Low,i.e., the same as the sampling result RSMP0, then clock OVCO is earlierthan input data IN.

FIG. 3 is a graph of waveforms illustrating the timing relationship(e.g., how late/early) between clock OVCO and input data IN based ondifferent phase clocks of clock OVCO, in accordance with someembodiments. In some embodiments, input data IN is phase locked to the90° phase of signal OVCO. Stated another way, the data edge DE isaligned to the rising edge of clock Clk_90, but so that the phasedetector PD operating in the areas neighboring the rising edge of clockClk_90 (e.g., regions I and II) is not disturbed, the phase lockassistant PLA is configured to operate in regions III and IV (e.g., thesignal comparisons are performed in regions III and IV). Even though thecomparison regions are shifted from regions I and II to regions III andIV, the comparison results indicating the timing relationship betweenclocks OVCO and input data IN are the same as if the comparisons areperformed in the regions I and II.

The line “Clk_0 to data” showing regions late_a and early_a indicateswhether clock OVCO is late or early with respect to input data IN usingthe rising edge of clock Clk_0 as a reference. The regions late_a andearly_a are determined using clocks Clk_0, Clk_90 and Clk_180 samplinginput data IN as illustrated in FIG. 2. For simplicity, clock Clk_180 isnot shown. For example, if data edge DE is between times t1 and t3, t5and t7, and t9 and t11, clock OVCO is later than input data IN. If,however, data edge DE is between times t3 and t5, t7 and t9, clock OVCOis earlier than input data IN.

The line “Clk_45 to data” showing regions late_b and early_b indicateswhether clock OVCO is late or early with respect to input data IN usingthe rising edge of clock Clk_45 as a reference. The regions late_b andearly_b are determined using clocks Clk_45, Clk_135 and Clk_225 samplinginput data IN as illustrated in FIG. 2 wherein clocks Clk_45, Clk_135and Clk_225 correspond to clocks Clk_0, Clk_90 and Clk_180,respectively. For simplicity, clock Clk_225 is not shown. For example,if data edge DE is between times t2 and t4, t6 and 18, and t10 and t12,clock OVCO is later than input data IN. If the data edge DE, however, isbetween times t4 and t6, t8 and t10, clock OVCO is earlier than inputdata IN.

In some embodiments, a combination of the regions late_a, early_a,late_b, and early_b are used to determine the timing relationship (e.g.,late/early) between clock OVCO and input data IN and the movingdirection of input data IN with respect to clock OVCO. For example, ifusing the two sets of clocks Clk_0, Clk_90 and Clk_180, and Clk_45,Clk_135 and Clk_225 to sample data edge DE, and the results reveal thatdata edge DE is in the region III (e.g., between times t4 and t5 orregions early_a and early_b) in a first clock cycle (e.g., cycle n−1)and in the region IV (e.g., between times t5 and t6 or in regions late_aand early_b) in a subsequent cycle (e.g., cycle n), then input data INis moving from the left to the right passing time t5 or input data IN islater than clock OVCO. In contrast, if the sampling results reveal thatinput data IN is in the region IV (e.g., late_a and early_b) in cyclen−1 and in the region III (e.g., early_a and early_b) in cycle n, thendata IN is moving from the right to the left passing time t5 or inputdata IN is earlier than clock OVCO. Once the relationship is determined,appropriate signals (e.g., signals UP and DN in FIG. 7) are generatedaccordingly to increase or decrease the frequency of clock OVCO.

Exemplary Method

FIG. 4 is a flowchart 400 illustrating how signals (e.g., signals UP andDN) are generated to increase/decrease the frequency of clock OVCO, inaccordance with some embodiments. For illustration, regions I, II, III,IV, V correspond to the regions between times t2 and t3, t3 and t4, t4,and t5, t5 and t6, and t6 and t7, respectively. Alternatively expressed,regions I, II, III, IV, and V correspond to the regions late_a andlate_b, early_a and late_b, early_a and early_b, late_a and early_b, andlate_a and late_b, respectively.

In block 405, if condition 1 is true, that is, if input data IN is inregion V (e.g., late_a and late_b) in clock cycle n−1 and in region IV(e.g., late_a and early_b) in clock cycle n, then input data IN ismoving from the right to the left passing time t6, which indicates thatclock OVCO is later than input data IN. As a result, phase lockassistance PLA in step 407 generates a logical “1” for the “UP” signal(FIG. 7) of signal OPLA so that charge pump PLA CP generates acorresponding signal OCP to increase frequency FVCO making clock OVCOfaster. Method 400 then flows to step 430 where the clock cycle n isincreased (e.g., n=n+1), or, stated another way, the clock proceeds tothe next cycle.

If condition 1, however, is not true, then in step 410, if condition 2is true, that is, if input data IN is in region III (e.g., early_a andearly_b) in cycle n−1 and in region II (e.g., early_a and late_b) incycle n, then input data IN is moving from the right to the left passingtime t2, which indicates that clock OVCO has been aligned (e.g., phaselocked) with data IN. As a result, phase lock assistant PLA in step 412generates a logical “0” for the UP signal so that charge pump PLA CPgenerates a corresponding signal OCP to not increase frequency FVCO.Clock OVCO and input data IN are now aligned (e.g., phase locked).

In some embodiments, the method 400 loops through steps 405, 407, and430 many times before proceeding to step 410 then step 412. Expresseddifferently, initially clock OVCO is later than input data IN, and ittakes many clock cycles for input data IN to transition through regionsIV and III before reaching region II or for PLA to increase frequencyFVCO many times before data edge DE is aligned with the rising edge ofclock Clk_90.

In block 415, if none of the condition 1 or condition 2 is true, and ifcondition 3 is true, that is, if input data IN is in region II (e.g.,ealry_a and late_b) in clock cycle n−1 and in region III (e.g., early_aand early_b) in clock cycle n, then input data IN is moving from theleft to the right passing time t2, which indicates that clock OVCO isearlier than input data IN. As a result, phase lock assistance PLA instep 417 generates a logical “1” for the “DN” signal (FIG. 7) of signalOPLA so that charge pump PLA CP generates a corresponding signal OCP todecrease frequency FVCO making clock OVCO slower. Method 400 then flowsto step 430 where the clock proceeds to the next cycle.

If condition 3, however, is not true, then in step 420, if condition 4is true, that is, if input data IN is in region IV (e.g., late_a andearly_b) in cycle n−1 and in region V (e.g., late_a and late_b) in cyclen, then input data IN is moving from the left to the right passing timet6, which indicates that clock OVCO has been aligned with input data IN.As a result, phase lock assistant PLA in step 412 generates a logical“0” for the DN signal so that charge pump PLA CP generates acorresponding signal OCP to not decrease frequency FOVCO. Clock OVCO anddata IN are now aligned (e.g., phase locked).

In some embodiments, the method 400 loops through steps 415, 417, and430 many times before proceeding to step 420 then step 422. Expresseddifferently, initially clock OVCO is earlier than input data IN, and ittakes many clock cycles for input data IN to transition through regionsIII and IV before reaching region V or for PLA to decrease frequencyFOVCO many times before data edge DE is aligned with the rising edge ofclock Clk_90.

The Phase Detector Circuit

FIG. 5 is a detailed schematic diagram 500 of phase detector PD (e.g.,PD 500) in accordance with some embodiments. Flip-flops FF, Exclusive-ORgates XO and AND gates AD are means for PD 500 to use clocks Clk_1,Clk_2, and Clk_3 to sample data Data and generates signals Late andEarly as illustrated in FIG. 2. Clocks Clk_2 and Clk_3 are 180° and 90°out of phase with clock Clk_1, respectively. If the sampling result ofclock Clk_3 is the same as the sampling result of clock Clk_2, thenclock Clk_1 is later than Data, and signal Late is generated (e.g.,high). But if the sampling result of clock Clk_3 is the same as thesampling result of clock Clk_1, then clock Clk_1 is earlier than Dataand signal Early is generated “true.” If signal Early is true, thencharge pump PD CP generates an “dn” signal OCP for low pass filter LPFto decrease frequency FVCO, but if signal Late is true, then charge pumpPD CP generates a “up” signal OCP for low pass filter to increasefrequency FVCO.

In some embodiments, PD 500 is also used in phase lock assistant PLA(FIG. 7). Consequently, clocks Clk_1, Clk_2, and Clk_3 correspond toclocks Clk_0, Clk_180, and Clk_90, data Data correspond to input data INand signals Late and Early correspond to the respective regions late_a,early_a in FIG. 3. As a result, signals (e.g., signals late_A andearly_A) are generated corresponding to the regions late_a and early_a,respectively, based on the results of clocks Clk_0, Clk_90, and Clk_180sampling input data IN. In some further embodiments, clocks Clk_1,Clk_2, and Clk_3 correspond to clocks Clk_45, Clk_225, and Clk_135, dataData correspond to input data IN and signals Late and Early correspondto the respective regions late_b, early_b in FIG. 3. As a result,signals (e.g., signals late_B and early_B) are generated correspondingto the regions late_b and early_b, respectively, based on the results ofclocks Clk_45, Clk_135, and Clk_225 sampling input data IN.

In some embodiments, PD 500, based on signals Q_1 and Q_2, alsogenerates signal Toggle for use in FIG. 7 below.

FIGS. 6A-6D show truth tables 600A-D illustrating an operation of PD 500of FIG. 5 in accordance with some embodiments. Truth tables 600A-Cillustrate the operation of the respective outputs Q_1, Q_2, and Q_3having data Data and the respective clocks Clk_1, Clk_2, and Clk_3 asinputs. In tables 600A, 600B, and 600C, the respective outputs Q_1, Q_2,and Q_3 follow the input Data at the rising edge of the respectiveclocks Clk_1, Clk_2, and Clk_3, and are unchanged otherwise. Truth table600D shows the operation of signals Late and Early having signals Q_1,Q_2, and Q_3 and Clk_1 as inputs. Signals Late, Early, and Toggle areunchanged when clock Clk_1 is at a constant level Low or High, and areat a logic level Low or High at the rising edge of clock Clk_1 as shownin the table.

The Phase Lock Assistant Circuit

FIG. 7 is a block diagram 700 of phase lock assistant PLA (e.g., PLA700) in accordance with some embodiments. In some embodiments, phasedetector PD1 and PD2 are implemented using PD 500. Phase detector PD1uses clocks Clk_0, Clk_90, and Clk_180 to sample input data IN andgenerate signals early_A and late_A corresponding to the regions early_aand late_a as illustrated in FIGS. 2 and 5. Phase detector PD2 usesclocks Clk_45, Clk_135, and Clk_225 to sample input data IN and generatesignals early_B and late_B corresponding to the regions early_b andlate_b as illustrated in FIGS. 2 and 5. Clocks Clk_45, Clk_135, andClk_225 correspond to clocks Clk_0, Clk_90, and Clk_180, and clocksClk_1, Clk_3, and Clk_2, respectively. Additionally, phase detector PD1generates signal Toggle_a to activate circuit UPDOWN and thus signals UPand DN when input data IN is transitioning (e.g., from a low to a highor from a high to a low).

Circuit UPDOWN01 receives input signals early_A, late_A, early_B,late_B, and clock Clk_0 as inputs and generates outputs Up_1, Up_0,Dn_1, and D_0. In some embodiments, circuit UPDOWN01 includescombinatorial logic circuitry. In some further embodiments, circuitUPDOWN01 is a state machine.

Circuit UPDOWN receives input signals Up_1, Up_0, Dn_1, Dn_0, andToggle_a, and generates signal UP and DN.

FIG. 8 is a block diagram 800 illustrating a detailed diagram of circuitUPDOWN01 in FIG. 7, in accordance with some embodiments.

Circuits B1, B2, B3, and B4 generate signals Up_1, Dn_1, Up_0, and Dn_0,respectively. Each circuit B1, B2, B3, and B4 is implemented from acircuit “BB” (shown in FIG. 9 below) having the same input terminals A,B, C, D, and clock, and generating an output Q. As a result, circuitsB1, B2, B3, and B4 function in the same way except that they eachreceive different inputs at their input terminals and generate differentoutputs at respective output terminals Q. For example, circuit B1receives inputs Late_A, Late_B, Late_A, and Early_B at the respectiveterminals A, B, C, and D, and generates signal Up_1. Circuit B2 receivesinputs Early_A, Late_B, Early_A, and Late_B at the respective terminalsA, B, C, and D, and generates signal Dn_1 at the respective outputterminal Q, etc. In some embodiments, each circuit B1, B2, B3, and B4 isa state machine.

FIG. 9 is a detailed diagram 900 illustrating an implementation of acircuit BB of FIG. 8, in accordance with some embodiments. Nodes A_FFand B_FF are the internal outputs of circuit 900 (e.g., the outputs ofthe respective flip flops FF). Circuit 900 receives inputs A, B, C, andD and clock Clk_0, and, using flip-flops FF and a four-input AND gateAD4, generates an output Q.

FIGS. 10A-10C show the truth tables 1000A, 1000B, and 1000C illustratingan operation of circuit BB in FIG. 9, in accordance with someembodiments. In table 1000A, output A_FF depends on input signal A andclock Clk_0. In some embodiments, at the rising edge of clock Clk_0,output A_FF follows input A (e.g., output A_FF is High if input A isHigh, and output A_FF is Low if input A is Low). When clock Clk_0 is ata constant level (e.g., Low or High), output A_FF is unchanged.Similarly, in table 1000B, output B_FF depends on input signal B andclock Clk_0. In some embodiments, at the rising edge of clock Clk_0,output B_FF follows input B (e.g., output A_FF is High if input A isHigh, and output B_FF is Low if input A is Low). When clock Clk_0 is ata constant level (e.g., Low or High), output A_FF is unchanged. In table1000C, output Q depends on signals A_FF, B_FF, C, and D. Output Q isHigh when all signals A_FF, B_FF, C, and D are high. Otherwise, output Qis low.

FIG. 11 is a detailed diagram 1100 of circuit UPDOWN in FIG. 7 (e.g.,circuit 1100), in accordance with some embodiments. Signal UP isgenerated based on signals Up_0 and Up_1 passing through OR gate ORUPand AND gate ANDUP and flip-flops FFUP. Similarly, signal DN isgenerated based on signals Dn_0 and Dn_1 passing through OR gate ORDNand AND gate ANDDN and flip-flops FFDN. Signals UP and DN are activatedwhen signal Toggle_a is activated (e.g., high, when input data IN istransitioning).

FIGS. 12A-12D show truth tables 1200A, 1200B, 1200C, and 1200Dillustrating an operation of circuit 1100 in accordance with someembodiments. In table 1200A, signal UP_int depends on signals Up_0,Up_1, and clock Clk_0. Signal UP_int is unchanged when clock Clk_0 is ata constant level (e.g., Low or High) or both signals Up_0 and Up_1 areLow. At the rising edge of clock Clk_0 signal UP_int is Low when signalUp_0 is High, and signal UP_int is High when signals UP_0 and UP_1 areLow and High, respectively. In table 1200B, signal UP depends on signalsUP_int, Toggle, and Clk_0. Signal UP is unchanged when clock Clk_0 is ata constant level High or Low. At the rising edge of clock Clk_0, signalUP is High when both signals UP_int and Toggle are High, and is Lowotherwise.

In table 1200C, signal DN_int depends on signals Up_0, Up_1, and clockClk_0. Signal DN_int is unchanged when clock Clk_0 is at a constantlevel Low or High, or both signals Dn_0 and Dn_1 are Low. At the risingedge of clock Clk_0 signal DN_int is Low when signal Dn_0 is High, andsignal DN_int is High when signals DN_0 and DN_1 are Low and High,respectively. In table 1200D, signal DN depends on signals DN_int,Toggle, and Clk_0. Signal DN is unchanged when clock Clk_0 is at aconstant level High or Low. At the rising edge of clock Clk_0, signal DNis High when both signals DN_int and Toggle are High, and is Lowotherwise.

A number of embodiments have been described. It will nevertheless beunderstood that various modifications may be made without departing fromthe spirit and scope of the invention. The above method embodiments showexemplary steps, but they are not necessarily performed in the ordershown. Steps may be added, replaced, changed order, and/or eliminated asappropriate, in accordance with the spirit and scope of the disclosedembodiments. Each claim of this document constitutes a separateembodiment, and embodiments that combine different claims and/ordifferent embodiments are within the scope of the disclosure and will beapparent to those of ordinary skill in the art after reviewing thisdisclosure.

What is claimed is:
 1. A method for a circuit having a phase lockassistant circuit that receives an input signal and a feedback clocksignal having a first phase, a second phase, a third phase, a fourthphase, and fifth phase, and a sixth phase corresponding to a first phaseclock, a second phase clock, a third phase clock, a fourth phase clock,a fifth phase clock, and a sixth phase clock, respectively, the methodcomprising: using the first phase clock, the third phase clock and thefifth phase clock to sample the input signal and generate a firstrelationship between the feedback clock signal and the input signal anda second relationship between the feedback clock signal and the inputsignal; using the second phase clock, the fourth phase clock, and thesixth phase clock to sample the input signal and generate a thirdrelationship between the feedback clock signal and the input signal anda fourth relationship between the feedback clock signal and the inputsignal; and generating a fifth relationship between the feedback clocksignal and the input signal based on the first relationship, the secondrelationship, the third relationship and the fourth relationship;wherein the first phase, the second phase, the third phase, the fourthphase, the fifth phase and the sixth phase are in an order of phasedegree.
 2. The method of claim 1 wherein the first phase, the secondphase, the third phase, the fourth phase, the fifth phase and the sixthphase are at phases of 0°, 45°, 90°, 135°, 180°, are at 225°,respectively.
 3. The method of claim 1 wherein generating the fifthrelationship comprises: generating the first relationship based on aresult of the first phase clock sampling the input signal and a resultof the third phase clock sampling the input signal; generating the thirdrelationship based on a result of the fifth phase clock sampling theinput signal and the result of the third phase clock sampling the inputsignal; generating the second relationship based on a result of thesecond phase clock sampling the input signal and a result of the fourthphase clock sampling the input signal; and generating the fourthrelationship based on a result of the sixth phase clock sampling theinput signal and the result of the fourth phase clock sampling the inputsignal.
 4. The method of claim 1 further comprising: generating a firststate of a signal if the second relationship and the fourth relationshipoccurs in a first clock cycle and the second relationship and the thirdrelationship occur in a second clock cycle subsequent to the first clockcycle; and generating a second state of the signal if the firstrelationship and the third relationship occur in a third clock cycle andthe first relationship and the fourth relationship occur in a fourthcycle subsequent to the third clock cycle; wherein the third clock cycleis subsequent to the second clock cycle.
 5. The method of claim 1further comprising: generating a second state of a signal if the firstrelationship and the fourth relationship occur in a first clock cycleand the first relationship and the third relationship occur in a secondclock cycle subsequent to the first clock cycle; and generating a secondstate of the signal if the second relationship and the thirdrelationship occur in a third clock cycle and the second relationshipand the fourth relationship occur in a fourth cycle subsequent to thethird clock cycle; wherein the third clock cycle is subsequent to thesecond clock cycle.
 6. A circuit comprising: a first circuit configuredto lock a frequency of an output clock to a frequency of a referenceclock; a second circuit configured to align an input signal to a phaseclock of the output clock; a third circuit configured to use a first setof phase clocks of the output clock and a second set of phase clocks ofthe output clock to improve alignment of the input signal to the phaseclock of the output clock; and a lock detection circuit configured toturn on the first circuit when the frequency of the output clock is notlocked to the frequency of the reference clock; and to turn off thefirst circuit and to turn on the second circuit and the third circuitwhen the frequency of the output clock is locked to the frequency of thereference clock.
 7. The circuit of claim 6 wherein the third circuitcomprises: a fourth circuit configured to receive the first set of phaseclocks and the input signal and generate a first early signal indicatingthe output clock is earlier than the input signal and a first latesignal indicating the output clock is later than the input signal; and afifth circuit configured to receive the second set of phase clocks andthe input signal and generate a second early signal indicating theoutput clock is earlier than the input signal and a second late signalindicating the output clock is later than the input signal.
 8. Thecircuit of claim 7 wherein the third circuit further comprises: a sixthcircuit configured to receive the first early signal, the first latesignal, the second early signal, the second late signal, a clock in thefirst set of phase clocks to generate a first up signal corresponding toa first state of a first signal, a second up signal corresponding to thesecond state of the first signal, a first down signal corresponding to afirst state of a second signal, and second down signal corresponding toa second state of the second signal; and a seventh circuit configured toreceive the first up signal, the second up signal, the first downsignal, the second down signal, the clock in the first set of phaseclocks, and a toggle signal generated by the fourth circuit to generatethe first signal and the second signal.
 9. The circuit of claim 7wherein the fourth circuit is configured to generate the first earlysignal when a first result of a first clock of the first set of phaseclocks sampling the data is the same as a second result of a secondclock of the first set of phase clocks sampling the data and generatethe first late signal when the second result is the same as a thirdresult of a third clock of the first set of phase clocks sampling thedata, and the fifth circuit is configured to generate the second earlysignal when a first result of a first clock of the second set of phaseclocks sampling the data is the same as a second result of a secondclock of the second set of phase clocks sampling the data and generatethe first late signal when the second result of the second clock of thesecond set of phase clocks sampling the data is the same as a thirdresult of a third clock of the second set of phase clocks sampling thedata.
 10. The circuit of claim 6 wherein the first set of phase clocksincludes a 0° phase clock, a 90° phase clock, and a 180° phase clock,and the second set of phase clocks includes a 45° phase clock, a 135°phase clock, and a 225° phase clock.
 11. The circuit of claim 10 whereinthe third circuit is configured to use the 0° phase clock, the 90° phaseclock, and the 180° phase clock to generate a first early signalindicating the output clock is earlier than the input data and a firstlate signal indicating the output clock is later than the input data,and the third circuit is configured to use the 45° phase clock, the 135°phase clock, and the 225° phase clock to generate a second early signalindicating the output clock is earlier than the input data and a secondlate signal indicating the output clock is later than the input data.12. The circuit of claim 11 wherein the third circuit is configured touse the first early signal, the first late signal, the second earlysignal, the second late signal, and the 0° phase clock to generate afirst signal and a second signal used to improve the alignment of theinput signal to the phase clock of the output clock.
 13. The circuit ofclaim 6 wherein the third circuit is configured to improve the alignmentof the input signal to the phase clock of the output clock by increasinga frequency of the output clock if the output clock is slower than theinput signal and by decreasing the frequency of the output clock if theoutput clock is faster than the input signal.
 14. The circuit of claim13 further comprising a charge pump circuit configured to receive anoutput signal of the third circuit to increase the frequency of theoutput clock if the output clock is slower than the input signal and todecrease the frequency of the output clock if the output clock is fasterthan the input signal.
 15. The circuit of claim 14 further comprising alow pass filter circuit configured to receive an output signal of thecharge pump circuit to increase the frequency of the output clock if theoutput clock is slower than the input signal and to decrease thefrequency of the output clock if the output clock is faster than theinput signal.
 16. A circuit comprising: a first circuit configured toreceive an input signal and first phase, third phase, and a fifth phaseclocks of a clock, and generate a first early signal indicating theclock is earlier than the input signal and a first late signalindicating the clock is later than the input signal; a second circuitconfigured to receive the input signal and second phase, fourth phase,and sixth phase clocks of the clock, and generate a second early signalindicating the clock is earlier than the input signal and a second latesignal indicating the clock is later than the input signal; the firstphase clock, the second phase clock, the third phase clock, the fourthphase clock, the fifth phase clock and the sixth phase clock are in anorder of phase degree; and a third circuit configured to receive thefirst early signal, the first late signal, the second early signal, thesecond late signal, and the first phase clock, and generate a firstsignal and a second signal that are used to align the input signal andthe clock; the first circuit is configured to use the first phase clockto sample the input signal and result in a first phase clock result, touse the third phase clock to sample the input signal and result in athird phase clock result, to use the fifth phase clock to sample theinput signal and result in a fifth phase clock result, and to generatethe first early signal when the first phase clock result is the same asthe third phase clock result, and to generate the first late signal whenthe fifth phase clock result is the same as the third phase clockresult; and the second circuit is configured to use the second phaseclock to sample the input signal and result in a second phase clockresult, to use the fourth phase clock to sample the input signal andresult in a fourth phase clock result, to use the sixth phase clock tosample the input signal and result in a sixth phase clock result, and togenerate the second early signal when the second phase clock result isthe same as the fourth phase lock result, and to generate the secondlate signal when the sixth phase clock result is the same as the fourthphase clock result.
 17. The circuit of claim 16 wherein the thirdcircuit comprises: a fourth circuit configured to receive the firstearly signal, the first late signal, the second early signal, the secondlate signal, and the first phase clock and generate a first up signal, asecond up signal, a first down signal, and a second down signal; and afifth circuit configured to receive the first up signal, the second upsignal, the first down signal, the second down signal, the first phaseclock, and a toggle signal generated by the first circuit, and generatethe first signal and the second signal.
 18. The circuit of claim 16wherein the first phase clock, the second phase clock, the third phaseclock, the fourth phase clock, the fifth phase clock and the sixth phaseclock are 0°, 45°, 90°, 135°, 180°, and 225° phase clocks, respectively.19. The circuit of claim 16 wherein the clock is a feedback clock.
 20. Acircuit comprising: a first circuit configured to lock a frequency of anoutput clock to a frequency of a reference clock; a second circuitconfigured to align a phase clock of the output clock to an inputsignal; a third circuit configured to use a first set of phase clocks ofthe output clock and a second set of phase clocks of the output clock toimprove alignment of the input signal to the phase clock of the outputclock; and a lock detection circuit configured to turn on the firstcircuit when the frequency of the output clock is not locked to thefrequency of the reference clock; and to turn off the first circuit andto turn on the second circuit and the third circuit when the frequencyof the output clock is locked to the frequency of the reference clock.21. A circuit comprising: a first circuit configured to lock a frequencyof an output clock to a frequency of a reference clock; a second circuitconfigured to align a phase clock of the output clock to an inputsignal; a third circuit configured to use a first set of phase clocks ofthe output clock and a second set of phase clocks of the output clock toimprove alignment of the input signal to the phase clock of the outputclock; and a lock detection circuit configured to turn on the secondcircuit and the third circuit responsive to an output signal of the lockdetection circuit.
 22. A circuit comprising: a first circuit configuredto receive an input signal and first phase, third phase, and fifth phaseclocks of a clock, and generate a first early signal indicating theclock is earlier than the input signal and a first late signalindicating the clock is later than the input signal; a second circuitconfigured to receive the input signal and second phase, fourth phase,and sixth phase clocks of the clock, and generate a second early signalindicating the clock is earlier than the input signal and a second latesignal indicating the clock is later than the input signal; the firstphase clock, the second phase clock, the third phase clock, the fourthphase clock, the fifth phase clock and the sixth phase clock are in anorder of phase degree; and a third circuit configured to receive thefirst early signal, the first late signal, the second early signal, andthe second late signal, and at least one of the first, second, third,fourth, fifth, and sixth phase clock, and generate a first signal and asecond signal that are used to align the input signal and the clock; thefirst circuit being configured to: sample the input signal based on thefirst phase clock and generate a first phase clock result; sample theinput signal based on the third phase clock and generate a third phaseclock result; sample the input signal based on the fifth phase clock andgenerate a fifth phase clock result; and generate the first early signalwhen the first phase clock result is the same as the third phase clockresult, and generate the first late signal when the fifth phase clockresult is the same as the third phase clock result; and the secondcircuit being configured to: sample the input signal based on the secondphase clock and generate a second phase clock result; sample the inputsignal based on the fourth phase clock and generate a fourth phase clockresult; sample the input signal based on the sixth phase clock andgenerate a sixth phase clock result; and generate the second earlysignal when the second phase clock result is the same as the fourthphase clock result, and generate the second late signal when the sixthphase clock result is the same as the fourth phase clock result.